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Ordering number : EN*4982A
CMOS LSI
LC82101
Image Processing Circuit for FAX, Copier, and OCR Products
Preliminary Overview
The LC82101 converts an analog image signal from a CCD or contact sensor to high-quality binary image data. The LC82101 uses an internal 8-bit A/D converter for A/D conversion, and in addition to the orthodox dithering technique, also supports an error diffusion technique that allows an even higher quality image to be acquired. These techniques apply to the whole range of processing supported by the LC82101, including full-pixel distortion correction, gamma conversion for arbitrary gamma curves, image compression processing, two-dimensional filtering, halftone processing, and image separation processing to separate documents into text, photograph, and halftone regions. Thus this LSI implements the image processing required by FAX, copier, and OCR systems. * Halftone processing Structural dithering (64 levels), settable dithering threshold level Error diffusion technique (64 levels) * Image reduction (thinning, fine black line retaining, fine white line retaining) * Single-voltage 5 V supply and low power due to CMOS process fabrication
Package Dimensions
unit: mm 3174-QFP80E
[LC82101]
Features
* Number of pixels processed 2048 pixels/line (64 KB memory, white correction only) 4096 pixels/line (256 KB memory, both white and black correction) 8192 pixels/line (256 KB memory, white correction only) * Processing speed 500 ns/pixel maximum (The processing time for 1 pixel is 16/SYSCLK.) * Supports medium speed products with a single external memory chip 100 ns access time memory allows 800 ns/pixel processing, and 60 ns access time memory allows 500 ns/pixel processing. * AGC (The A/D converter high-level reference voltage is varied from 1.2 to 4.2 V in 0.2 V steps.) * Built-in 8-bit A/D converter (includes a sensor signal delay adjustment function) * Sensor drive circuit (supports CCD and all CIS types) * Digital clamp (single-point clamp, even/odd clamp) * Distortion correction (white correction, black correction, full-pixel correction) * Gamma correction (supports user-defined curves) * Image area separation (text, photographs, halftone) * Simple binary-conversion processing (fixed threshold level, density-adaptive threshold level)
SANYO: QIP80E
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
63095HA (OT) No. 4982-1/5
LC82101 Block Diagram
Pin Functions
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol DREQ ACK PD0 PD1 PD2 PD3 PD4 PD5/SDE PD6/SDCK PD7/SD MD0 DVDD DGND MD1 MD2 MD3 MD4 MD5 MD6 MD7 DGND MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 I/O O I O O O O O O O O B P P B B B B B B B P O O O O O O O O O External memory address MA14 is the MSB and MA0 is the LSB. Digital system ground External memory data bus MD7 is the MSB and MD0 is the LSB. Pin 8 can be switched to function as the serial data output valid period signal. Pin 9 can be switched to function as the serial data transfer clock. Pin 10 can be switched to function as the serial data output. External memory data bus Digital system power supply Digital system ground Binary image data parallel data bus The data order is set by the MSBF register. DMA data request signal output DMA acknowledge signal input Function
Continued on next page. No. 4982-2/5
LC82101
Continued from preceding page.
Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection Pin No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol DVDD DGND MA9 MA10 MA11 MA12 MA13 MA14 MCS MRD MWR DGND MTP SH RS CLK1 CLK2 CLK3 SAMP CLKIN DVDD DGND NC NC NC TEST AGND ATAP AIN TEMP AVDD RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RA0 RA1 RA2 DVDD DGND RA3 RA4 CS READ WRITE RESET I/O P P O O O O O O O O O P O O O O O O O I P P NC NC NC I P O I I P B B B B B B B B I I I P P I I I I I I Digital system power supply Digital system ground CPU interface address bus CPU interface CS signal CPU interface READ signal CPU interface WRITE signal System reset CPU interface address bus RA4 is the MSB and RA0 is the LSB. CPU interface data bus RD7 is the MSB and RD0 is the LSB. Test input (Connect to ground in normal use.) Analog system ground Analog mid-level connection Sensor signal input Temperature signal input Analog system power supply Sampling clock monitor System clock input Digital system power supply Digital system ground Sensor drive signal outputs External memory CS signal External memory READ signal External memory WRITE signal Digital system ground Motor drive timing signal output External memory address bus MA14 is the MSB and MA0 is the LSB. Digital system power supply Digital system ground Function
No. 4982-3/5
LC82101 Sample Application Circuit
1. C1: Use a 0.01 F laminated ceramic capacitor. 2. Set up the polarity of the image signal from the sensor so that white data is represented by the highest potential and black data by the lowest potential. A level conversion circuit can allow the whole dynamic range of the built-in A/D converter to be used effectively if the maximum output level of the peaks in the image signal from the sensor does not reach 4.2 V. 3. When a 64 K SRAM is used as the distortion correction memory, leave MA11 and MA12 unused and connect MA13 and MA14 to the memory A11 and A12 lines. 4. Although AGND and DGND are completely isolated internally in this LSI, AVDD and DVDD are connected through the substrate. Therefore, the power supply system must be designed so that no potential difference between AVDD and DVDD can occur. Also, when power is applied or removed, the time lag between the power supplies must be under 3 ms.
No. 4982-4/5
LC82101
Specifications
Absolute Maximum Ratings at Ta = 25C, GND = 0 V
Parameter Maximum supply voltage I/O voltages Allowable power dissipation Operating temperature Storage temperature Soldering conditions Symbol VDD max VI, VO Pd max Topr Tstg Hand soldering: 3 seconds Reflow soldering: 10 seconds Ta 70C Conditions Ratings -0.3 to +7.0 -0.3 to VDD + 0.3 450 -30 to +70 -55 to +125 350 235 Unit V V mW C C C C
Allowable Operating Conditions at Ta = -30 to +70C, GND = 0 V
Parameter Supply voltage Input voltage Symbol VDD VIN Conditions min 4.5 0 typ max 5.5 VDD Unit V V
DC Characteristics at Ta = -30 to +70C, GND = 0 V, VDD = 4.5 to 5.5 V
Parameter Input high-level voltage Input low-level voltage Input leakage current Output high-level voltage Output low-level voltage Output leakage current Current drain Symbol VIH VIL IL VOH VOL IL IDD VIN = VDD, VSS IOH = 3 mA IOL = 3 mA When in the high-impedance state VDD = 5.0 V, SYSCLK = 32 MHz -100 40 -25 2.4 0.4 +100 60 Conditions min 2.2 0.8 +25 typ max Unit V V A V V A mA
Analog Characteristics The minimum signal level in analog input signals must be matched to AGND, and the maximum signal level must not exceed the maximum AGC potential.
Parameter [When AGND = 0 V] Maximum potential Minimum potential [When AVDD = 5.0 V, AGND = 0 V, and the AGC is at the maximum potential] Resolution Linearity error Differential linearity error 8 1 1 bit LSB LSB 0.82 0.22 0.84 0.24 0.86 0.26 AVDD V AVDD V Symbol Conditions min typ max Unit
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of June, 1995. Specifications and information herein are subject to change without notice. PS No. 4982-5/5

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